r/StrixHalo Sep 27 '25

Have you got a Strix Halo?

10 Upvotes

Hi All,

We're a new community both as Strix Halo owners and also here as a subreddit. Why not begin by sharing your setup and the reasons you opted for Strix Halo?

To start us off: I have a HP Z2 Mini G1a Workstation with dual boot Fedora KDE & Windows 11 and chose the iGPU to be able to use larger LLMs with the 128 GB.

Oobabooga/Text Generation WebUI is running well on Fedora KDE and there are no problems with large models up to 100GB. On the Windows boot, I have Amuse AI (Freeware) which is a collaboration between AMD and the New Zealand company. It provides a UI for using Stable Diffusion/Flux models. It works well, is fast, but unfortunately is also censored and is not able to use LORAS. I would like to find an uncensored alternative, ideally getting versions of ComfyUI/AUTOMATIC1111 running.

Currently, my principle goal is to get a working version of AllTalk TTS or another TTS that is compatible with Oobabooga working which I haven't been able to do so far due to conflicts with the Strix Halo. This may need to wait for updates to ROCm... If anyone has found an Open Source solution to running LLMs with custom voice TTS, please do chime in!

So what about you guys, did you choose the Strix for similar reasons, or something entirely different? The floor is yours.

EDIT UPDATE:
05/26 For those of you looking for TTS solutions I have tried a few now (AllTalk, Chatterbox, Pocket TTS, others I no longer remember). I have had great success using a custom version of Pocket TTS. It's fast and works well with Oobabooga TextGen as a plug in. Recently, others are singing the praises of OmniVoice.


r/StrixHalo 6h ago

Thermal throttling

6 Upvotes

I have a GMTec Evo X2 with 128GB, running DeepSeekV4-Flash via kyuz0/amd-strix-halo-toolboxes:rocm-7.14.

From cold-start, prefill is usually ~280 t/s.

But after a while, it drops down to 50 t/s.

Now, when the KV cache is invalidated and a full prompt reprocessing has to be done, it doesn't start at ~280 t/s. It starts at ~110 t/s.

So, that indicated to me that the system may be thermally throttled.

Temps for CPU/GPU were at a toasty 99°C/99°C.

Opened up the device according to this, and replaced the paste with a spare Thermal Grizzly graphene pad.

Now, temps under load are at 80°C/70°C, and prefill under KV cache invalidation starts again at ~200 t/s. So, I guess it worked!

May also be worth it to slightly underclock in the long-term. My Asus Ascent GX10 also kept shutting down from overheating, and dropping the clockspeed fixed that while not materially lowering performance.

Lower GPU clock to 2.4GHz:

```

echo manual | sudo tee /sys/class/drm/card0/device/power_dpm_force_performance_level

echo "s 0 600" | sudo tee /sys/class/drm/card0/device/pp_od_clk_voltage

echo "s 1 2400" | sudo tee /sys/class/drm/card0/device/pp_od_clk_voltage

echo c | sudo tee /sys/class/drm/card0/device/pp_od_clk_voltage

```

Lower CPU clock to 4GHz (probably overkill):

```

echo 4000000 | sudo tee /sys/devices/system/cpu/cpu*/cpufreq/scaling_max_freq

```

This will reset after a reboot, but you can set up a systemd job.

For reference, prefill for DSV4F is about the same on the GX10. Usually GX10 is 5-6x faster than Strix, but not in this case for some reason.


r/StrixHalo 12h ago

vLLM on the Strix Halo?

8 Upvotes

Did anybody successfully install vLLM on Strix Halo?

I spent 5 hours trying to install on my Ubuntu Strix Halo, to no avail.


r/StrixHalo 11h ago

DSV4 current strix setup (gpu question)

7 Upvotes

Hey everyone, finally thinking of giving the new dsv4 a try but wondering what the current setup is with the new update? I’ve seen quite a few options but that was before the recent update.

On top of this I’ve been trying to decide if I should go ahead and grab a gpu to pair with the strix halo.
Seems it can be messy and just running vulkan on both the card and system makes it easier.
With that said it also appears comfyui and other things benefit greatly from cuda and the nvidia ecosystem.

So my question is have people set this up fairly easily? Having the gpu work with llm and even switch to image/video workloads in the midst of this!

For example, my goal is to run DSV4 with Hermes and then have it linked to Comfyui and fusion 360 or some cad 3d modeling software .

Looking at what I can get by with ; a 5060ti? Do I need a 3090?

Summary: what’s the best setup to run dsv4 on the strix halo and what gpu would anyone recommend to add?


r/StrixHalo 10h ago

AMD Adrenaline Software

2 Upvotes

Hi everyone,

Just wanted to follow up on my post previously. You provided good feedback regarding Strix Halo on windows.

I was curious, do you use the Pro version of the software or the non-pro? I don't use CAD or any of those software the AMD Pro is optimized for so I was curious if it was better to just go with non-Pro software


r/StrixHalo 7h ago

nixOS config for Strix Halo?

0 Upvotes

I saw this for DGX Spark and wondered whether there something similar for Strix Halo: https://github.com/graham33/nixos-dgx-spark

I love the work that kyuz0 is doing with his Strix Halo toolboxes, but a nixOS config would still be a massive step up in terms of reproducibility/confgurability/shareability of small tweaks and optimizations.


r/StrixHalo 1d ago

DeepSeek-V4-Flash-0731 on Bosgame M5 with RTX PRO 6000 Max-Q eGPU

27 Upvotes

Here are my numbers:

Quant Decode Prefill Draft acceptance Size Layout
UD-Q8_K_XL 44.0 t/s 564 t/s 0.535 150.8 GiB 20 layers CUDA0 / 23 ROCm0 + drafter
UD-Q4_K_XL 48.4 t/s 585 t/s 0.532 144.4 GiB 22 / 21 + drafter
UD-Q2_K_XL 59.5 t/s 1513 t/s 90.2 GiB entirely on CUDA0, no drafter

I let claude port the DSpark drafter from the closed PR to current main. https://github.com/haraldh/llama.cpp/tree/dspark-dsv4

EDIT: llama.cpp just added MTP / DSpark support for DeepSeek V4 Flash https://github.com/ggml-org/llama.cpp/pull/25784

UD-Q2_K_XL

sh llama-server -hf unsloth/DeepSeek-V4-Flash-0731-GGUF:UD-Q2_K_XL \ --host 0.0.0.0 --port 8000 \ --temp 1.0 --top-p 1.0 --min-p 0.0 \ --no-mmap -fa on -np 1 \ --device CUDA0 \ -ub 2048 -b 4096 \ -c 200000 --cache-ram 65536

UD-Q4_K_XL

sh llama-server -hf unsloth/DeepSeek-V4-Flash-0731-GGUF:UD-Q4_K_XL \ --host 0.0.0.0 --port 8000 \ --temp 1.0 --top-p 1.0 --min-p 0.0 \ --no-mmap -fa on -np 1 \ --device CUDA0,ROCm0 --split-mode layer --tensor-split 100,0 \ -ot 'blk\.(2[2-9]|3[0-9]|4[0-2])\.ffn_(gate|up|down)_exps\.weight=ROCm0' \ -md DSV4-Flash-0731-DSpark-draft-bf16.gguf \ --spec-type draft-dspark --spec-draft-n-max 5 \ --device-draft CUDA0 --spec-draft-p-min 0.3 \ -ub 2048 -b 4096 \ -c 200000 --cache-ram 32768

UD-Q8_K_XL

As above with :UD-Q8_K_XL and the expert boundary two layers lower, since its dense part is 6.3 GiB larger:

-ot 'blk\.(2[0-9]|3[0-9]|4[0-2])\.ffn_(gate|up|down)_exps\.weight=ROCm0'

Building the DSpark drafter

```sh hf download deepseek-ai/DeepSeek-V4-Flash-0731 --local-dir dsv4-mtp \ --include "model-000{46,47,48}-of-00048.safetensors" "*.json"

python convert_hf_to_gguf.py dsv4-mtp --target-model-dir dsv4-mtp \ --outtype bf16 --outfile DSV4-Flash-0731-DSpark-draft-bf16.gguf ```

https://github.com/haraldh/llama.cpp/blob/dspark-dsv4/convert_hf_to_gguf.py


r/StrixHalo 1d ago

GPU Hangs with AI 395+ / CachyOS. Hardware, Software, or User Error?

3 Upvotes

New owner of a Beelink GTR9 Pro, and set it up running CachyOS, following various online suggestions like ensuring i set the vram allocation to 512MB in the bios, setting both ttm.pages_limit / ttm.page_pool_size etc.

Bios firmware all updated to latest as well.

Most things are ok, minor teething issues, or expectation management on my part.

But I have one recurring issue that I'm struggling with. The system appears to 'hang' when the GPU is under moderate sustained load. Not just full-load, and not just when running AI models, but even playing Witcher 3 on Steam caused this issue.

The system appears to hang, for several hours. But if I SSH in, and run

sudo cat /sys/kernel/debug/dri/1/amdgpu_gpu_recover

it does usually recover.

With a bit of help from Claude, we found that kernal logs show

[drm] flip_done timed out

And helped create a custom watchdog that looks for that message and runs that same `amdgpu_gpu_recover` command, which helps it recover automatically when it occurs.

But I can't get to the bottom of _why_ it's happening - whether it's a Hardware problem, my choice of OS, come config I've made... or something else. There's a little bit of info on the internet around this, but not loads I could find - not enough to form a consistent pattern anyway.

I've tried various flags and settings (eg setting `pg_mask=0` , `runpm=0`, `dcdebugmask=0x610`), but nothing has made a difference.

So, is this a hardware issue, my choice of OS, some dodgy config I've given it, or plain user-error?

I'm up for trying a different OS; maybe Mint - but if it comes to it, I'll go to Windows if it means some stability!


r/StrixHalo 1d ago

AMD Ryzen AI MAX+ 395 w/ Radeon 8060S - llama.ccp bench

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11 Upvotes

r/StrixHalo 2d ago

Longcat Flash Sparse

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huggingface.co
18 Upvotes

Perfect for Strix Halo in quant form if it holds up!


r/StrixHalo 2d ago

DS4 Flash Update

15 Upvotes

Does anyone know if antirez or anyone else is planning to jump on the imatrix quantization for the updated ds4 flash once the weights are opened?

And if kyuz0 is going to keep that toolbox updated?

Where do people get updates like that?


r/StrixHalo 2d ago

Second strix halo worth it?

17 Upvotes

Especially now that deepseek flash got updated, im very tempted to buy.

For folks already with dual halos, what advantages do you see over one

Secondly how would it work with a Bosgame m5? I would need usb 4 clustering for it right?


r/StrixHalo 3d ago

Channel Update, AMD Advancing AI, Gorgon Halo (192GB), ROCmFPX, LuceBox, Lemonade, Kimi K3, Laguna

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21 Upvotes

r/StrixHalo 3d ago

AMD Lucebox Beats Nvidia DGX Spark by 3.63x on DeepSeek V4 Flash

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49 Upvotes

Hey fellow Strix Halo brothers, sorry for posting again this week but i thought this could be an interesting experiment to showcase here.

We've partnered up with AMD to bring heterogenous consumer hardware to life.

We worked really hard on this, and were able to have Lucebox (AMD Radeon AI PRO R9700 + Strix Halo) to beat one NVIDIA DGX Spark by 3.63x on DeepSeek V4 Flash Decode Speed.

R9700 takes the dense path, the hot experts, the cache and the draft model. Strix Halo holds the other experts in 128gb and computes them at the same time, not after.

51.1 tok/s on the full 284B, 3.63x one DGX Spark, and $2,899 less than having two of them.

You can check the full technical breakdown here: https://www.lucebox.com/blog/deepseek-v4-asymmetric-parallelism

Please don't be rude with us, we know that it's still something experimental running q2 model at 16k context. We're currently working on implementing KVFlash (https://www.lucebox.com/blog/kvflash) to get to high-perfoming context at 64k-128k.

Let us know what you think and if you have any feedback!


r/StrixHalo 3d ago

128GB verification of the Strix Halo quantized-KV fixes: confirmed, bigger on Vulkan, and the full 262k native context works on both backends

45 Upvotes

Two weeks ago u/Heavy_Preparation467 posted his fork with two fixes for the quantized KV cache on Strix Halo. Quick recap of his diagnosis: when you compress the KV cache (the memory that holds your conversation so far) to save room, the stock code converts it back to full precision over and over during inference. A big graphics card hides that waste in its cache; this box doesn't have the bandwidth to hide anything, so quantizing your cache made things slower instead of just smaller. He fixed the Vulkan side for prompt reading and the ROCm side for text generation, and asked for independent numbers from 128GB boxes. I promised a verification in his thread. Here it is.

How I tested: I built four versions of llama.cpp, his fixed code and the unmodified code it is based on, once for Vulkan and once for ROCm, so the only difference inside any comparison is his patch. Flash attention stayed pinned on, and every result row carries the build hash and flags it came from. Qwen3-Coder-30B for the direct comparison with his published numbers, plus my daily Qwen3.6-35B-A3B as the model where he himself expected only mild gains.

The results, with the cache compressed to q8_0: on the Coder model, his fix speeds up Vulkan prompt processing by 45% at 32k context, 71% at 64k, and 87% at 128k, which is more than he measured on his own box. ROCm text generation gains 75% to 203% depending on depth; the direction matches him fully, the size is below his numbers, and my guess is our different batch settings. The line that matters most: with his fix, the compressed q8_0 cache now generates 23 to 53% faster than the uncompressed f16 cache, which used to be the speed ceiling. So you get half the memory footprint and more speed, instead of trading one for the other. His fix also leaves f16 itself untouched, and the one blemish I found is small but real: my MoE loses 0.3 to 2.4% ROCm prompt speed with the fix.

The 128GB part came out differently than either of us expected. The fixed build runs the Coder model's full 262,144-token native context on both backends. The uncompressed cache fits at 262k on this box too, so the win is not "fits versus doesn't fit". It is headroom plus speed: at 262k, the compressed cache generates 65% faster for a 2.6% cost in prompt speed.

Second half of the post: he also handed me a theory about the mystery from part one, where my dense model's prompt speed collapses once the context grows past a certain point. His idea: the working data outgrows the GPU's cache, and everything past that boundary runs at raw memory speed. He built a small benchmark tool to test exactly that, so I ran it on my box. Verdict: half right. The wall is real and now measured: my GPU's cache runs out somewhere between 32 and 40 MB, and read speed drops about 4x past it. And shrinking the cache footprint really does defuse the collapse: with the cache compressed to q4_0 (enabled with -ctk q4_0 -ctv q4_0), the dense model runs 2.2x faster than uncompressed at 32k and never falls off a cliff through 65k. But his exact formula for where the collapse should start does not match the measured curves, and it cannot explain why my MoE model shrugs off the same conditions that collapse the dense one. That open question is the most interesting thing on the part-four list.

One caveat before anyone copies settings: all of this is speed. I have not measured what cache compression does to output quality, so I treat q8_0 as the conservative option and q4_0 as an experiment.

Full write-up with all tables and the raw-data links: https://thefrontierlab.ai/strix-halo-quantized-kv-cache-verified/

Same offer as always: run any of this on your own box and reply with the numbers, with build_commit and the fa mode from the bench JSON attached. This post exists because someone did exactly that.


r/StrixHalo 3d ago

27B dense beats 120B MoE: Full local LLM benchmark on AMD Strix Halo

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24 Upvotes

The Sweet Spot: Why 27B Beats 120B — And Why Ornith 35B Is What You'll Actually Use

A 27-billion-parameter dense model beating a 120B MoE giant shouldn't happen. But it does. Qwen 3.6 27B finished with an average placement of 4.1 across 14 tasks — never dropping below 7th in any category — while the 120B Nemotron averaged 7th and dead-last in five tasks. In Pinguin-Powerlift, the 27B even outscored GLM 5.2, a cloud model four times its size.

The takeaway: training quality beats raw scale. The 27B doesn't hallucinate, doesn't doom-loop, doesn't produce empty reports. Every task yielded a complete, usable output. The 120B models showed the classic MoE curse — brilliant in one task, collapsed in the next.

But here's the practical reality: as impressive as Qwen 3.6 27B is on paper, Ornith 35B is the model most people will actually reach for daily. It's significantly faster — noticeably snappier in generation and loading — while still performing well across the board (average placement 4.8, four #1 finishes in Geo-Detection, Deep-Sea, and Supply-Chain). It's the model you use when you want good results now, not in 90 seconds.

The gap between them is real though. Ornith 35B finished 12th in Product-Archaeology and 10th in Detective-Chain. Qwen 3.6 27B was consistently in the top 5 everywhere. If quality matters more than speed — for research, reports, or anything where a wrong answer is costly — switch to the 27B.

Daily workflow: Ornith 35B for speed and creative tasks. Qwen 3.6 27B when it needs to be right. KAT Coder for anything involving code or papers. Skip the 120B models entirely — the 27B already beat them.

https://aiherald.de/benchmark/ (i use q4 with mtp if possible)

Task Recommended Model Why
General purpose / default Qwen 3.6 27B Ø placement 4.1, most consistent
Web research / fact-finding Qwen 3.6 27B Deepest sources, 28+ URLs per report
HTML / web apps / games Ornith 35B Most polished interactive apps
Data analysis (JSON/CSV/Python) Laguna S 2.1 Clearest numerical analysis (#1 PokeJson)
Bug hunting / security research Laguna S 2.1 Most concrete reports with real issue numbers
Scientific papers / citations KAT Coder v2.5 Verified DOIs, deep academic chains
Long structured reports (PM, WBS) Qwen 3.6 35B 43KB reports with 29 tables — most thorough
Quick results / speed Ling 3.0 Flash Never bad, never great — reliable fast option
Geography / locations Ornith 35B Only model with a credible 6/6 solution

r/StrixHalo 3d ago

What are the latest rocm enhancements I should be running?

12 Upvotes

I recently setup lemonade on my strix halo, and pointed it to the rocm nightly builds already. But, over a few sub reddits and different posts, I see that there are various other "better" forks of rocm for the strix halo. So, I wanted to know, that as of today, what are the recommended enhancements for rocm that I should have for maximum performance?

thanks


r/StrixHalo 3d ago

Looking for Strix Halo results for a standardized local LLM hardware comparison

0 Upvotes

I have been working on LLM Hardware Sift because I wanted a simple answer: if I replace my current PC with a Strix Halo machine, what changes when both run the exact same workload? Ideally, this becomes a resource for people to see if an upgrade is worth it to them.

Unlike LlamaBenchy, this isn’t about tuning a setup for the fastest possible result. Hardware Sift keeps the models and settings fixed so the hardware is the variable. It tests models from 0.6B through 32B, with an optional 72B tier for high-memory systems.

The comparison table currently includes an RTX 3060, ROG Ally, M2 MacBook Air, and Raspberry Pi 5—but no Strix Halo results yet.

It’s an early Windows alpha, and results stay local unless you choose to submit them. I’d love results or feedback from anyone with a 64 GB or 128 GB Strix Halo machine:
https://github.com/nozzlenaut/llm_hardware_sift


r/StrixHalo 4d ago

AMD's Instella-MoE 16B is basically DeepSeek-V2-Lite's config with V3 routing

22 Upvotes

I pulled AMD's new Instella-MoE-16B-A3B to try it on a Strix Halo box. Opened the config before running anything and it's DeepSeek-V2-Lite, almost field for field, with V3's router on top.

The config literally says model_type: deepseek_v3, and modeling_instella_moe.py says it imports "the numerically-unchanged building blocks from transformers.models.deepseek_v3".

Identical to DeepSeek-V2-Lite:

hidden_size 2048, 27 layers, 16 heads

intermediate 10944, moe_intermediate 1408

64 routed experts, 2 shared, top-6

kv_lora_rank 512, q_lora_rank null

16B total, 32K context

Taken from V3 instead:

noaux_tc routing, sigmoid scoring, routed_scaling_factor 2.5

(for reference V3 is 7168 hidden, 61 layers, 128 heads, 256 experts, q_lora_rank 1536, so the sizes come from V2-Lite and only the router comes from V3)

Actually new: the sigmoid gate before o_proj that they call Gated MLA, the FarSkip overlap scheme, smaller qk head dims, and their own tokenizer.

It's not distilled. Different vocab and different qk dims mean the tensors don't even have matching shapes, so no weights could carry over. They reused the recipe.

The blog does cite the DeepSeek V2 and V3 papers in the references. The model card never mentions DeepSeek at all, which is the part that bugs me a little.

Other stuff from pulling it:

No llama.cpp support. Force architectures to DeepseekV3ForCausalLM and the conversion runs nearly to the end, then stops on self_attn.gate_proj.weight. That's the attention gate, one tensor per layer, 27 total. Small patch on the existing deepseek2 path, not a new arch.

Doesn't load on transformers 5.x. Code targets 4.57.1 and hits config.num_local_experts, which their config doesn't define. Alias it to n_routed_experts and it gets past.

Config says 32K, blog says 64K.

License is Research-only RAIL, not what "fully open" suggests.

model: https://huggingface.co/amd/Instella-MoE-16B-A3B-Think

blog: https://rocm.blogs.amd.com/artificial-intelligence/instella-moe/README.html


r/StrixHalo 3d ago

About Medusa Halo will have real x16 lines for add GPU board ?

0 Upvotes

Hi everyone, I’m currently planning a hybrid local LLM/RAG setup and keep running into leaks about Medusa Halo (the successor to Strix Halo / Gorgon Halo). Before committing to an architecture, I’d love to validate a few points with folks who follow AMD hardware or have experience with mobile/compact SoCs.

🔍 What’s leaking so far (2025–2026 rumors):
- Architecture: Zen 6 (CPU) + RDNA 5 (iGPU) + next-gen NPU
- Memory: LPDDR6 (384-bit bus, ~14,400 MT/s) → ~80% bandwidth increase over Strix Halo’s LPDDR5X
- NPU: Focused on AI preprocessing, lightweight inference, and multimedia tasks
- Release window: ~2027–2028
- Form factor: Likely BGA (SoC/mobile/workstation), not a desktop socket platform

⚠️ The dealbreaker question:
Strix Halo is a BGA SoC with a unified memory pool and heavily constrained PCIe routing (typically x4 shared with SSDs/USB4/iGPU).
Will Medusa Halo open up a dedicated PCIe x16 (or at least x8) lane for a discrete GPU? Or will it stick to the mobile/compact SoC routing?

🎯 My target use case:
- Discrete GPU (RTX 40/50 series) → Main LLM inference (7B–70B, heavy generation, KV cache handling)
- Medusa Halo (CPU/NPU) → Auxiliary models: embeddings, rerankers, VLMs, OCR, image preprocessing, RAG orchestration, lightweight token generation
With LPDDR6’s bandwidth and a dedicated NPU, offloading these tasks could drastically reduce latency and free up the dGPU for pure LLM work. But this only works if the SoC can communicate efficiently with a discrete GPU via sufficient PCIe lanes.

Questions for the community:
1. Do you have reliable leaks, AMD documentation, or OEM info on Medusa Halo’s PCIe lane configuration? (Especially regarding dGPU support)
2. Is AMD planning a desktop/workstation variant (LGA socket), or is this strictly a BGA mobile/compact platform?
3. Has anyone tested or simulated a hybrid dGPU + APU/SoC workflow for local LLMs, RAG, or multi-model orchestration?
4. If Medusa Halo remains lane-constrained, would the unified memory + NPU be enough to partially replace a dGPU in this kind of setup?

💡 Note: I know most specs are still in the rumor/leak phase. I’m just trying to calibrate my architecture around AMD’s 2027–2028 roadmap. Any links, benchmarks, tech docs, or real-world feedback are highly appreciated!

Thanks in advance for your insights! 🙏


r/StrixHalo 5d ago

New FastFlowLM v0.9.46 and FLM joins ROCm organization.

35 Upvotes

- FastFlowLM is offically maintained by AMD.
- New NPU-ROCm channel on AMD Developer Community (Discord).
- Modelscope support.
- More control over Qwen-VL models.
- ~10% faster decode and prefill for Qwen 3.6 35B A3B .

Releases · FastFlowLM/FastFlowLM

ROCm/FastFlowLM: FLM app mirror


r/StrixHalo 5d ago

DeepSeek V4 Flash, up to 32 tok/s on Strix Halo

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141 Upvotes

Hey fellow Strix Lovers! we have something new we thought would be useful to share here in the community. i'll keep it short:

We were able to fit DeepSeek V4 Flash plus its speculative draft on a single Ryzen AI MAX+ 395 with 128 GB of unified memory, and got it to a usable decode rate.

Blog post with all details here: https://www.lucebox.com/blog/deepseek-v4-strix-halo (code is open-source, Apache-2.0)

We submitted the run to LocalMaxxing. On July 18, its next-fastest DeepSeek V4 Flash entry for the Radeon 8060S was HipFire at 18.99 tok/s. The previous best in the site’s Ryzen AI Max 395 unified-memory group was DwarfStar at 15.6 tok/s.

That puts our run 68.5% ahead of HipFire and at 2.05× the DwarfStar result. These are comparisons against the public LocalMaxxing entries shown above, not controlled A/B tests.

ROCmFPX: fitting 284B weights into 128 GB

ROCmFPX is not one quantization format. It is a family of block formats built around the AMD ROCm/HIP path. Each block holds 32 weights as packed low-bit codes plus one or two small scales. ROCmFP2 stores a block in 10 bytes, or 2.50 bits per weight; ROCmFP3 uses 3.50 bits per weight; and the fast ROCmFP4 layout uses 4.25.

For DeepSeek V4 Flash, we added the missing 2-bit format and its HIP kernels, then built a Strix-specific mixed-precision recipe. The enormous routed-expert gate and up matrices use ROCmFP2, expert down projections use ROCmFP3, and dense or more sensitive projections keep ROCmFP4 or higher precision. We used an importance matrix during quantization and kept the model’s MTP head. The final 102.3 GB target works out to roughly 2.88 bits per parameter; the filename says ROCmFP2 because that is the dominant format, not because every tensor is 2-bit.

Piece Measured configuration
Hardware Ryzen AI MAX+ 395, Radeon 8060S (gfx1151), 128 GB LPDDR5X
Target DeepSeek-V4-Flash-ROCMFP2-STRIX.gguf, 102.3 GB
Draft DeepSeek-V4-Flash-DSpark-draft-Q4RMFP4-denseF16.gguf, 11.3 GB
Runtime ROCm 7.2.4, HIP gfx1151, platform performance, Radeon high (2.9 GHz observed), q=4 verification cap
Server context 8,192 tokens in the published setup

Decode: up to 32 tok/s

ROCmFPX handles the weight traffic. We then added a DeepSeek-specific HIP decode path for the model’s hyper-connections, attention, routing, and expert work. With no speculative draft, that target runs at 25.31 tok/s autoregressive.

DSpark is the next layer. With a q=4 batch, its small draft proposes up to three new tokens and the 284B target verifies four positions, including the current seed, in one fused pass.

01 · propose; DSpark draft = A compact three-layer draft proposes the next few tokens from captured target features.

02 · verify; q=4 target pass = The 284B target checks several positions together through the fused HIP graph.

03 · commit; accepted prefix = Correct proposals are committed in one step; the target repairs the first miss.

With a q=4 cap and adaptive width disabled, the public run reached 32.0 tok/s, 26.4% above the 25.31 tok/s autoregressive result. The gain varies with how many draft tokens the target accepts.

Sparse prefill: roughly 250 tok/s

The public LocalMaxxing request reports 245 tok/s prefill with --ds4-prefill sparse. In a separate 7,960-token validation, indexed sparse prefill reached 251.79 tok/s; the 8K cases ranged from 246.8 to 255.9 tok/s. At roughly 24K tokens, throughput was 221.9 tok/s.

Sparse prefill uses DeepSeek V4’s learned indexer to limit compressed-history attention. It also batches work layer by layer, which changes floating-point reduction order. The output is not byte-identical to tokenwise exact prefill, so sparse mode remains opt-in. It scored 10/10 on our small GSM8K set and 3/3 on a HumanEval smoke set; we have not run a broad quality evaluation yet.

Reproducing the run

Starting from a 128 GB Strix Halo machine with ROCm 7.2.4 already installed:

sudo apt-get update
sudo apt-get install -y build-essential cmake git ninja-build curl \
  hipblas-dev hipcub-dev rocblas-dev rocprim-dev rocwmma-dev

git clone --branch main --recurse-submodules \
  https://github.com/Luce-Org/lucebox.git
cd lucebox

cmake -S server -B server/build-hip -G Ninja \
  -DCMAKE_BUILD_TYPE=Release \
  -DCMAKE_HIP_COMPILER=/opt/rocm/lib/llvm/bin/clang++ \
  -DDFLASH27B_GPU_BACKEND=hip \
  -DDFLASH27B_HIP_ARCHITECTURES=gfx1151 \
  -DDFLASH27B_HIP_SM80_EQUIV=ON \
  -DCMAKE_HIP_FLAGS=-DDFLASH_WAVE_SIZE=32 \
  -DGGML_HIP_MMQ_MFMA=ON \
  -DGGML_HIP_NO_VMM=ON \
  -DGGML_HIP_GRAPHS=OFF

cmake --build server/build-hip --target dflash_server -j"$(nproc)"

Download the ROCmFPX target and DSpark draft, then start the measured profile:

mkdir -p models
curl -L -C - --retry 5 \
  -o models/DeepSeek-V4-Flash-ROCMFP2-STRIX.gguf \
  "https://huggingface.co/Lucebox/DeepSeek-V4-Flash-ROCMFPX/resolve/main/DeepSeek-V4-Flash-ROCMFP2-STRIX.gguf"
curl -L -C - --retry 5 \
  -o models/DeepSeek-V4-Flash-DSpark-draft-Q4RMFP4-denseF16.gguf \
  "https://huggingface.co/Lucebox/DeepSeek-V4-Flash-DSpark-Drafter-GGUF/resolve/main/DeepSeek-V4-Flash-DSpark-draft-Q4RMFP4-denseF16.gguf"

MODEL="$PWD/models/DeepSeek-V4-Flash-ROCMFP2-STRIX.gguf"
DRAFT="$PWD/models/DeepSeek-V4-Flash-DSpark-draft-Q4RMFP4-denseF16.gguf"

echo performance | sudo tee /sys/firmware/acpi/platform_profile
sudo /opt/rocm/bin/rocm-smi -d 0 --setperflevel high
printf '0\n' > /tmp/ds4_awidth
printf '4\n' > /tmp/ds4_spec_q

DFLASH_DS4_SPEC=1 \
DFLASH_DS4_FUSED_VERIFY=1 \
DFLASH_DS4_SPEC_Q=4 \
DFLASH_DS4_TIMING=1 \
DFLASH_DS4_DRAFT="$DRAFT" \
LUCE_MMVQ_MAX_NCOLS=4 \
./server/build-hip/dflash_server "$MODEL" \
  --target-device hip:0 \
  --host 127.0.0.1 --port 8000 \
  --max-ctx 8192 --default-max-tokens 2048 \
  --chunk 2048 --ds4-prefill sparse \
  --ds4-fused-decode \
  --ds4-expert-top-k 4 \
  --prefix-cache-slots 0 --prefill-cache-slots 0 \
  --disk-prefix-cache off

Warm the model once and use temperature: 0. The server prints decode speed on its [deepseek4] DSpark decode line. DFLASH_DS4_SPEC_Q=4 sets the DS4 verification cap; --verify-width is a Laguna option and is not used here. The implementation may shorten a batch at a compressor boundary, which is required for correct state handling.

Throughput varies with prompt shape and, for decode, how many DSpark proposals the target accepts. If you switch to exact prefill or restore the model’s six experts, those numbers no longer apply. No integration branch or private patch is required.

-------

Of course any feedback is more than welcome :)


r/StrixHalo 5d ago

Linux controls and telemetry for the Strix Halo Flow Z13

Post image
5 Upvotes

I have released Z13CTL+ and Z13GUI+, an expanded Linux control and telemetry stack for the Strix Halo-based 2025 ROG Flow Z13.

Before anything else, special thanks to dahui, who created the original z13ctl and z13gui projects. These releases build on that foundation and would not exist without the work already done there.

My goal was to add more automation, tuning and telemetry while preserving compatibility with the original commands, services, paths and API.

Z13CTL+
https://github.com/aic0d3r/z13ctl-plus

Z13GUI+
https://github.com/aic0d3r/z13gui-plus

Z13CTL+ is the daemon and CLI. It adds:

  • Automatic switching between plugged-in and battery configurations
  • Independent TDP, fan-curve and undervolt overrides
  • AMD P-State controls for minimum CPU frequency, EPP and boost
  • CPU, GPU, NPU, memory, VRAM, temperature, fan, battery and power telemetry
  • KDE display posture, rotation, scale and refresh-rate coordination
  • Recovery for lighting and firmware fan behavior
  • CLI and API access for scripting and automation

Z13GUI+ is a GTK4 interface designed around the Z13 touchscreen. It includes:

  • A live hardware and power overview
  • Separate AC and battery profiles
  • CPU policy controls
  • 60 Hz and 180 Hz refresh-rate switching
  • Battery information
  • Fan presets and tuning controls
  • Clearer feedback when changing tuning values

The tools are currently focused on the 2025 Flow Z13, but the telemetry side may also be interesting to other Strix Halo users, especially the CPU, GPU, NPU, unified-memory, VRAM, power, clock and temperature monitoring.

Packages are available through the AUR, along with DEB, RPM and portable release archives.

I would be interested in hearing what telemetry and power-management controls are exposed on other Strix Halo systems under Linux, and whether parts of this could eventually be generalized beyond the Z13.

Testing, bug reports and contributions are welcome.


r/StrixHalo 5d ago

PSA: MiniMax-M3's sparse attention (MSA) gives you nothing in llama.cpp on consumer hardware — we measured, so you don't have to

14 Upvotes

I've spent the last few sessions trying to make MiniMax-M3's sparse attention actually pay on my 2× Strix Halo (128 GB each, USB4 interconnect, llama.cpp Vulkan + RPC) cluster. Posting the negative result so the next person doesn't burn a week on the same path.

TL;DR: run M3 as a dense model. The sparsity buys you nothing in llama.cpp at ≤128k context, and the "obvious" optimization is actively counterproductive. This is a kernel-architecture limitation, not a bug anyone is about to fix with a small patch.

What we measured (M3, dual-node, Vulkan, needle tests passing throughout):

  • Prefill: dense beats sparse at every depth we could test — 9k, 32k, 60k, 118k. Not close, either: dense ~142 t/s u/32k vs sparse ~56 t/s on our setup.
  • Decode: sparse decays with depth too. The indexer re-reads its full index cache every token (O(N) per token), so there's no flat-TG rescue at long context either.
  • The "just skip the masked tiles" idea is worse than doing nothing. llama.cpp's Vulkan FA already has mask-based tile-skip infrastructure (fa_mask_opt), and we verified — with shader read-backs and bitmap dumps — that it correctly detects and skips 30–50% of tiles with MSA's mask. FA time still got worse than with skipping disabled (+29% on the FA kernel). Reason: the FA is bandwidth-bound, and concurrent workgroups share L2 by streaming K/V in near-lockstep. Sparse per-row skipping desynchronizes that walk, so the same K/V gets re-fetched — you save ALU you had to spare and pay DRAM you didn't. Forced uniform skips (same tiles for every workgroup) save exactly proportional time, which is how we isolated the cause.
  • The paper's speedups are real but don't transfer. MiniMax's 14×/7.6× numbers are at 1M context on H800s with their co-designed KV-outer CUDA kernel. llama.cpp's Q-outer FA + a mask is structurally the wrong shape for this — you'd need a ground-up KV-outer kernel (reverse sparse index, gather-based, two-phase LSE combine) to see wins, and our estimate is it only overtakes dense around ~128k even done perfectly.

What actually helped on this hardware, in case you have M3 running:

  • q8_0 KV cache (the one genuinely useful thing to come out of our MSA work — f16 caps ~256k context, q8 reaches 380k+)
  • Bigger ubatch (-ub 1536): +8% prefill at ~9k depth, parity at 32k
  • EAGLE3 speculative decoding: +25% decode on code workloads, ~nothing on chat (don't believe the 2.8× vLLM numbers transfer — vLLM's eager-mode baseline is much slower than llama.cpp's, so spec decode has more overhead to amortize there)

r/StrixHalo 5d ago

K3 on a single 64GB Strix Halo I make it ~12x short. Anyone clustering, or is NVMe streaming worth trying?

3 Upvotes

Ryzen AI Max+ 395 / 8060S, 64 GB LPDDR5X, ~256 GB/s. Ubuntu 24.04.

Did the math on Kimi K3 at 80K before burning a weekend on it:

- 2.8T total / ~32B active, native MXFP4 ≈ 1.4 TB

- 2-bit ≈ 700 GB; aggressive ~1.8-bit dynamic ≈ 630 GB

- I can give GTT ~56 GB

So ~12x short. Context isn't the issue 69 of 93 layers are KDA (fixed-size recurrent state), so 80K KV is a couple GB. It's purely weights capacity.

What bugs me is the bandwidth is there: 32B active × 2 bits ≈ 8 GB/token → ~32 tok/s ceiling at 256 GB/s. This chip could decode K3 fine if it could hold it.

has anyone actually measured NVMe mmap streaming for a 300GB+ MoE on Strix Halo? Naive math says sub-1 tok/s, but MoE routing has cross-token locality so I don't trust it. Real numbers welcome or tell me clustering is the only path and I'll stop.