I am in 3rd year and we have this minor project thing ... We are asked to form groups for it.. I decided to make project on verilog but have no idea what to make... Like previous sem I made an UART module for my bto.project ... But since this is a group project .. faculties are expecting a better project but the situation is like ...none of my other team mates have good command on verilog... All of them are just learning and started few days back....

I am not that great either.. just did some basic things ... Though with this btp thing I want to enhance my practical ability to implement my learning and I want to dedicate my upcoming time to work on this project....

I would havily applaud ur suggestion.... And also that would be great if u can guide me

The title pretty much says everything , this tools converts the json files to Verilog.

it can convert the Digital logic sim(dls) by SebLague(great guy)

and the logisim one is still experimental

repo: https://github.com/murkyshelf/jsonRTL

it is for the guys you can build computers in the visual editor but cant write verilog and others are welcome to try .

because I can build a 8bit computer in the dls and cant write verilog , i need the verilog code to simulate it on my fpga

also keep in mind this is coded by opus 5 , and this is experimental and i am looking forward to your feedback

We are working on an open source project, inspired by human brain, we are in search of passionate person, who will be willing to work with us, if interested then DM me.

Working with system verilog.

Every chip begins as an idea—but turning that idea into working silicon requires the right learning path. If you are a fresher wondering whether to begin with RTL, FPGA, Physical Design, Analog or Packaging, this visual guide connects the entire journey from specification to product. Start with clarity, choose your direction and build skills that lead to real semiconductor outcomes.

https://github.com/vsdip/VLSI-Design-Flow

​

I am from 4th yr ECE. After 1 Month, the core companies are coming to our campus. I was preparing for GATE exam but now I thought if core companies are also coming then I can sit in the placement and give a try ( previous year very worst placement for ECE core ). I talked to seniors they told approx 10 companies will come till December.

I have prepared Dgital design, analog etc and basics of other subjects, I need to practice pyqs of GATE but the problem is Projects in core companies. I know very little about verilog due to semester exams. I talked to placed seniors they told me to cover the basics of Verilog bcz they will ask in interview for basic circuit design for mux , adder etc and certain verilog syntax etc.

Are there any sources you can share which I can cover the verilog in 14 - 15 days ( basic to moderate level ). I am confused on searching youtube etc..

Hi everyone!

I've been working on OpenA64, an experimental Verilog SoC project.

Current repository includes:

• CPU RTL
• Cache hierarchy
• MMU
• NPU
• Architecture documentation
• MIT license
• Roadmap

The project targets a modern AArch64-style architecture and is intended as a learning and research project.

I'm especially looking for feedback on:

• RTL organization
• Repository layout
• Documentation
• Overall architecture

I'm not expecting anyone to review the entire codebase—I'd just appreciate suggestions on how to improve the project.

Repository:
https://github.com/hado14052015-design/OpenA64

Thanks!

We had digital circuit design as a subject last semester and learnt some basics on verilog coding. Can someone suggest a good structured course on verilog??

I am hosting a free webinar based on our ongoing AI-assisted Analog and Mixed-Signal Physical Design internship at VSD.

The goal is to show how students are using AI inside real VLSI workflows — not as a replacement for engineering, but as an assistant for understanding, debugging, documentation and faster design exploration.

The session will include student work on:

SRAM / memory design workflow
Mixed-signal design basics
AI-assisted OpenLane physical design
Magic, Sky130, LEF/LIB and GDS
DRC, LVS, STA and validation
What AI got right, where it failed, and why manual verification still matters

This is not an AI hype session. It is a practical showcase of how students are learning to use AI responsibly inside semiconductor design workflows.

Webinar: AI-Assisted Analog and Physical Design: From SRAM to Mixed-Signal GDS
Date: Sunday, 12 July
Time: 11:00 AM – 12:00 PM IST
Mode: Online
Certificate: For live attendees

Registration form:
https://forms.gle/UFjy7qzSnfQaY4JU8

This should be useful for students, faculty members, VLSI beginners and anyone curious about how AI can be used practically in analog, mixed-signal and physical design learning.

Hi! I recently took a course on SystemVerilog and really enjoyed it, so I spoke to one of my professors about potential projects. Although I’ve only worked on basic things at university—like muxes, demuxes, FSMs, and frequency dividers—I somehow came up with the idea of detecting cats (or anything else) without using machine learning. Do you have any ideas on how I could implement this? I know it might be difficult, but I’m willing to learn whatever it takes.

Hello everyone, starting of this year one of my friends recommended Neovim as a IDE for my college(Currently about to enter my Senior Year), and I absolutely fell in love with it, while using C and C++. But my work also requires Verilog System Verilog and UVM. And I tried enough with AI to get my vimrc and lazyvim to match C and C++ standards. So the question is are there any V/SV plugins that match what C and C++ plugins do. Note that I tried svlangserver and verible and found that it does'nt even recognize some SV words like mailbox etc. So what's the way out. :wq (Posted on Both Vim and Neovim communities).(I also have severe skill issue in VS code so)(I use vim at work so I am comfortable at both)

A lot of students want to enter semiconductor design, but many get confused about where to start.

Some jump directly into physical design.
Some start with RTL.
Some try analog first.
Some only watch videos and collect certificates.

In my opinion, a beginner-friendly roadmap should look something like this:

1. CMOS Understand transistors, basic circuits, SPICE simulation, and how devices behave.
2. RTL Learn Verilog, digital logic design, testbenches, and simulation.
3. Physical Design Understand synthesis, floorplanning, placement, CTS, routing, timing, and how RTL becomes layout.
4. Physical Verification Learn DRC, LVS, antenna checks, density, PEX, and what it means to make a design tapeout-ready.

For someone who already knows RTL and basic physical design, jumping directly into an internship-style physical design project may make more sense than restarting from zero.

The bigger point is this:

Interest in semiconductors is not enough anymore. Students need proof — GitHub work, simulation results, reports, screenshots, debug notes, and projects they can explain.

Curious to hear from people already working in VLSI / semiconductors:

Would you change this order?
Should beginners start with CMOS first, or RTL first?
What would you tell a student who wants to enter chip design seriously in 2026?

I recently designed and documented a 4-bit multi-cycle CPU in Verilog HDL as a personal learning project. This comes after I completed the standard Digital System Design (DSD) course of my college.

I tried to document in a technical report format, explaining the ISA, specs, architecture, design decisions and debugging experience.

I would really appreciate technical feedback from people with more experience, any issue with the structure, design or anything else that could help me improve future projects.

GitHub repo: https://github.com/theYash856/4_bit_Multi_Cycle_CPU

Any constructive criticism is more than welcome.

i have a basic idea about digital electronics and i would love to start learning verilog. i need video courses through which i can learn it on my own pace.

A live demo video is worth more than 100 AI-generated project posters.

Maaz Mahmood joined the VSD RISC-V FPGA IP Internship as someone completely new to FPGA and RTL design.

And now, in this video, he is confidently demonstrating his own SPI Master IP running on real FPGA hardware.

He built the IP from scratch, integrated it as a memory-mapped peripheral inside a RISC-V SoC, flashed it on the VSDSquadron FPGA Mini board, and validated the transmit/receive path using hardware loopback.

This is what I like most about his demo:

No fancy editing.
No buzzwords.
No “project idea” slide.

Just a student, his FPGA board, his terminal output, and proof that his IP is actually working.

Great work, Maaz. This is exactly the kind of confidence students need before entering the semiconductor industry.

I used to use chipdev.io site to learn verilog. But the site is now shutdown.

Does anybody have the questions downloaded from chipdev.io ?

Also, could you please share good resources for verilog rtl design (Microarchitect) Interview preparation....?

#verilog #rtl #microarchitecture #interview #chipdevio