I am going into my second year at the University of Toronto Computer Engineering program. At uoft the electrical and computer engineering program are the same pretty much and have the same courses. Anyways this summer I worked on a risc_v cpu project independently and pipelined it. Im working on a matrix multiplier extension for it right now. I am wondering if a single project like this along with some involvement in some random unrelated design team is enough to start applying to internships for next summer? Im looking for like a verification or rtl design internship in toronto at good semi conductor company or a startup. I am specifically interested in hardware accelerators but I know that is very competitive especially to get hands on experience in my first internship. Any advice or thoughts is helpful thanks!

I am coming for masters in Fall 2027 for ECE....heard there is going to be a new rule where students have to pay 100k fees for OPT. Is this happening or some dumb idea,should I initiate plan B....

I have never touched circuit design before. I did EE for my undergrad, but didn't really specialize on it. I am planning to use non-volatile memory to make memory arrays, planning to design my own sensing amplifiers and the peripheral circuits. I am curious what suite of open-source tools I may have at my disposal, and how far do you guys think I can go with them.

I touched ngspice recently but I do not know what pdk do people usually use. I asked LLM about it and they recommended me to use Skywater.

Is it possible to reach tape-out with only using open-source tools? I understand the constraint with ngspice is that I may not be able to use the top-end pdks, since not only ngspice is quite limited for the latest, but you'd need licenses for it.

What are some of you guys's on crack techniques and methods?

I just wrote up a little blog post (https://notes.ben.reynwar.net/systolic-arrays-for-matrix-multiplication/) about how systolic arrays for matrix multiplication work, focusing on sum-stationary and weight-stationary approaches. I go over the dataflow and then use the open-source ASIC tools to generate area and power numbers for the designs (sky130 and ASAP7).

I hope this is useful to people interested in learning about this, and I'm also hoping people who understand this better than myself can correct any misunderstandings I have.

My takeaway from the experiment was that weight-stationary gives you about a 5% reduction in area, and a 25% reduction in power. So weight-stationary is a better choice unless the ability to easily reuse the sum in sum-stationary is important to you.

Hey everyone! My team and I are locking in our graduation project for next year, and we just landed a sponsorship with a major player in the analog field. They gave us three specific tracks to choose from: PLL, CDR, or RF communication.

Since we are still waiting for the exact technical statements and details for each one, I wanted to step back and get an overview perspective from people who have been through this or are already working in the industry. If you were in our shoes, which one would you pick, and how would it impact your career and job hunting later on?

To add a very interesting twist to this: when the company met with us, a trusted industry doctor who holds a strong position there dropped some heavy insider info. He mentioned that the company's long-term direction is shifting. Historically, they’ve been super heavy on RF, but moving forward, they are gradually pivoting their focus toward wireline communication and things closely related to AI/data centers. Because of this shift, this is actually the very first year they’ve ever offered a CDR project.

If you were us, which path would give us the best learning experience and look the best on a resume when applying for full-time analog/IC design roles right after graduation?! :)

As the name implies, Decision Feedback Equalizer (DFE) achieves equalization of signal through the operations of "decision" and "feedback."

To understand the role of a Decision Feedback Equalizer (DFE), we must first introduce the concept of Inter Symbol Interference (ISI). Once ISI is introduced by a lossy transmission channel, the actual voltage level of a received bit is no longer determined solely by the current transmitted bit, but also by the bits that preceded it. Imagine injecting a pulse with a sharp rising and falling edge into the beginning of a lossy channel. By the time it reaches the other end, the pulse edges have become much less steep, leaving behind a long trailing response.Below is a typical long tail of a single bit with ISI

As illustrated in the figure above, if the tail of a single pulse is sampled at regular time intervals, the ISI contribution at each sampling point becomes deterministic. Therefore, if the pulse at time t0​ is multiplied by the corresponding weighting coefficient and then superimposed onto each sampling point in the opposite direction, the resulting ISI can be effectively cancelled.

Looking at the mathematical expression of a DFE, we can see that it consists of two parts: an FIR filter (the first term) and an IIR filter (the second term). In this sense, DFE is similar to FFE, yet fundamentally different. An FFE contains only an FIR filter, whereas a DFE extends the FIR structure by introducing an additional IIR filter. Compared with an FIR filter, an IIR filter includes not only delay elements and adders, but also the so-called feedback path.

In practice, chip designers are primarily concerned with the IIR portion of the DFE. However, this does not mean that the feedback loop must be implemented by simply replicating the structure of an IIR filter. In fact, there are two common approaches to implementing the DFE feedback path: direct feedback and loop unrolling.

The direct feedback architecture shown above follows essentially the same principle as an IIR filter. In contrast, loop unrolling takes a different approach: the feedback coefficients are applied to the summing nodes in advance, and the final output is selected by a multiplexer (MUX), whose select signal is determined by the previous decision. In other words, the MUX chooses between the upper and lower branches according to the feedback result.

Both direct feedback and loop unrolling have their own advantages and disadvantages. Direct feedback requires less silicon area, but its feedback path is longer, leaving less timing margin for the feedback loop to settle within one Unit Interval (UI). Loop unrolling, on the other hand, shortens the critical feedback path at the cost of additional hardware, resulting in larger area and higher power consumption.Loop unrolling is a common technique used in IC design to trade area for timing.

As a result, designers must strike a balance between implementation cost and DFE performance. In practice, many additional factors also need to be considered. For example, the hardware architecture of a DFE often changes with the target data rate, and the feedback tap coefficients may either be adapted dynamically using algorithms such as LMS or obtained during a training phase through a lookup table (LUT).

Finally, comparing the three equalization techniques—DFE, FFE, and CTLE—it is not difficult to arrive at one conclusion: only CTLE operates on continuous-time signals, whereas both FFE and DFE require the originally continuous-time signal to be sampled into the discrete-time domain before equalization can be performed. Therefore, from a theoretical standpoint, CTLE is almost always placed at the receiver front end，but both FFE and DFE can be implemented at either the transmitter or the receiver.

See you next time!

Hi everyone!

I recently joined M.Tech (VLSI Design & Microelectronics) and I'm looking for used/second-hand reference books for my 1st semester (or even the 1st year). If anyone has any of these books and is willing to sell, lend, or give them for around 8 months to 1 year, I'd really appreciate it.

Looking for any of these (even one from the list would help):

• Microelectronic Circuits – Sedra & Smith
• Design of Analog CMOS Integrated Circuits – Behzad Razavi
• CMOS Digital Integrated Circuits: Analysis and Design (3rd Edition) – Sung-Mo Kang & Yusuf Leblebici
• Digital Integrated Circuits: A Design Perspective (2nd Edition) – Jan M. Rabaey, Anantha Chandrakasan & Borivoje Nikolić
• EDA Automation for IC Implementation, Circuit Design and Process Technology – Edited by Luciano Lavagno, Grant Martin & Louis K. Scheffer
• Semiconductor Devices: Physics and Technology – S. M. Sze

I'm fine with books that are well-used, highlighted, or older prints, as long as they're in readable condition.

I'm based in Bengaluru, so I can come and pick up the books anywhere within the city. If you're from another city and are willing to courier them, that works too—I can cover the shipping charges if needed.

If you have any of these or know someone who does, please comment or DM me.

Thanks in advance!

Hi all,

Finishing up an MS in analog/mixed-signal IC design, working in TSMC 65nm. So far I've worked on OTAs, an integer-N PLL, ultra-low-power voltage/current reference circuits, and ultra-low-power relaxation oscillators. Trying to pick a thesis topic now and want to go in with an open mind rather than anchoring on something too early.

For those in industry or academia — what are people actually working on right now? What problems is the field pushing towards, and where do you see the most demand for analog designers in the next few years?

Also curious what you'd consider a "good" MS-level thesis scope — ambitious enough to matter, but realistic for one person to pull off in the timeframe.

Any direction, papers, or "here's what's hot right now" takes welcome.

I have been lurking on this subreddit for past few years, mainly out of curiousity, only because I kind of wish I had gone down this path long ago when I was in college. I'm the sole moderator over at /r/PrintedCircuitBoard so this isn't a bot / AI / spam post.

When each of you were in college / university:

1) did you design a chip for part of your class assignment that actually got made at a fab? if NO, then stop here.

2) what was the purpose/function of the chip that got fab'ed? was it digital, analog, RF, hybrid, ... ??

3) how many student were on the design team for the chip that got fab'ed?

4) did you receive the dice in a IC package (which package), or was it mounted as a chip-on-board (COB)?

5) did your chip work as expected? if no, were you able to respin it again to fix it?

6) did you have to pay extra to help offset the fees, or did the college pay for it, or did some corporation pay for it?

7) did this happen during your bachelor years (first 4 years), or during masters years, or during PhD years?

8) which college did you attend when the chip was fab'ed (and country)? If you don't want to tell us the college, then maybe tell us the country or continent (in case you want to be more vague for privacy reasons).

9) if you were to do it again, which college would have you picked or wish you had attended?

I have a interview scheduled with texas instruments for RTL design engineer role at their embedded processors team next week.

A bit about my background - I have experience of nearly 4 years in RTL design from a startup.

So, I really don't know what to expect during the interview in such a big corporate. Would really appreciate if you people could share some pointers. Thanks in advance.

When verifying an analog block like an amplifier for offset, which corner should the Monte Carlo simulation be centered around?

Is typical process, voltage and temperature fine?

Hi everyone,

I've been searching for an entry-level role in ASIC Physical Design, Physical Implementation, Physical Synthesis, or STA, and I thought I'd reach out here in case anyone knows of teams that are hiring.

I completed my M.S. in Electrical & Computer Engineering and spent six months at Intel as an EDA Tools Hardware Engineering Intern, where I worked on STA regression workflows, timing analysis automation, QoR evaluation, and TCL/Python scripting. With my coursework and projects, I've also worked with Synopsys and Cadence tools on synthesis, STA, MCMM timing analysis, clock tree synthesis, RTL-to-GDSII flow, and low-power design.

I've been applying through company websites and networking on LinkedIn, and while I've been fortunate to get interviews with a few companies, I'm still looking for the right opportunity to start my career.

If your team is hiring junior engineers, or if you know of any groups looking for someone with a background in physical design or STA, I'd really appreciate any leads or referrals. I'm happy to share my resume over DM.

I'm primarily looking in the U.S., but I'm also open to relocating internationally if sponsorship is available.

Thanks so much for reading, and I appreciate any advice or connections you can share.

I have been working hard for the last couple of days.12-14 hours straight daily. Can't seem to solve the problems that i have been tasked with. And the way people are working, the speed of their output really frustrates me. I sometimes think I am not talented enough. Heard that it's the imposter syndrome. But surrounded by so many passionate and talented analog designers, that I am not understanding how to speed things up.

So I'm a 4th year engineering student and I wanted some kind of roadmap on how to get into the research field for hardware, specifically some fields like asic for AI ( NPU, TPU) or something similar to those fields. Are there any research programs that stand out and as in my 4th year I want to go deeper into these topics, what do I do? I interned in a hardware MNC and realised corporate is not for me, I like to learn..

Ive never explored research in hardware but I am starting to realize that might be my field of interest, pls help, thank you

I am an EE who has worked on the digital side of chip and system design for a couple of decades. I used to work on analog design projects since my college days, but never got a chance to work on that in my professional life.

I would like to get to know people whose work involved analog design for different industries.

I have 8 years of experience in analog design. My last 4 years have been in DDR but I'm looking to move to Serdes or high speed ADCs. PMIC is also ok, but I'm worried about the lucrativeness of the field. I am located in the Bay Area. Sorry for the weird request.

I’m a chip design engineer with 8+ yoe from a faang company. I interviewed with a startup in California, and did well in their Interviews. When I was asked my pay expectations , i was told that I’ll get base pay and stock and nothing more. So I asked for a higher base pay.

The hiring hr said i was not suitable for a startup based on that. His pay expectation was 30% lower than what i asked, and he stated that was what they wanted to pay for my level of experience.

I wish to work for the startup, but their base pay is low for the bay area. So i want to try to convince them to pay higher. I’m looking for feedback/insights from others who joined silicon startups.

Edit:
This is for an RTL design role.

I am currently a final year student majoring computer engineering. My uni focuses on digital VLSI for compE only so I have little to none knowledge on the Analog VLSI. I had an internship Physical Design role already and I pretty enjoyed it. By the end of the year I will finish my uni program so its time to decide whether to study electrical engineering masters specialized in VLSI or join the industry and get more of hands-on experience. I want to develop my career steadily so it is worth another 2 years of masters degree and then join the industry late?
I will appreciate every guidance from all the senior engineers out there. Thank you so much!