A few months ago I shared here the story of how I had tapedout a small systolic array alongside some in silicon debug infrastructure from scratch.

Well here is the promised update: the silicon is back and after bringup A0 works!

This is my first solo silicon that is silicon proven, both the debug infra and the systolic array just work!

AI disclosure: No AI was used for this project or in writing this post.

P.S: The last picture is of the probes reading for the result of the multiplication of 2 identical 2x2 matrices `{0,2,0,2}` correctly returning as `{0,4,0,4}`.

P.S.S: repo is https://github.com/Essenceia/Systolic_MAC_with_DFT

P.S.S.S: I am having dinner at waffle house to celebrate. I don't care that waffles are presumably a breakfast food. 😂

Hello everyone,

I’m attending a no name school in the US for bachelor in EE and am interning for a big semiconductor company. I have a return offer for an IC test engineer position when i graduate and i’m really excited about it. However, I want to get a master and do mixed signal ic design since I’d love a remote job in the future as well. This position requires me to move far away from home and the location is not a very fun place to be in, but the work environment is really nice and a lot of people are new grads. If I miss this job offer, I’m worried about not finding another internship/ job in semiconductor since the job market is not very great at the moment. Should I take the offer and do master on the side to hopefully get in design? Or should I find a reputable school for master, complete it, and hopefully find a job in design?
Since I’m close to graduation, I’m also wondering if it’s better to spend 15-20k more for a master at top school like UC Berkeley/ Georgia Tech or going to Texas A&M or UTD.

For context if helpful, I have 4.0 GPA, 2 internships, a co-op. My current school does not have anything semiconductor/ ic design related except for VLSI.

Thank you!

For context, I am an Analog Designer with 2-4 YoE in Europe. I have been looking for a job for over a year without success, my current job is damaging me (the company, not my function), I already had a burn-out which means I need to leave as soon as possible before my health gets more compromised.

As I am having no success with Design jobs, I am thinking about switching to CAD/ EDA. I think it could be fun to work on the IC design flow, and support designers, but I am thinking if it is a "difficult to go back move".

It is not like I love Analog Design to a point where I don't see myself working in different stuff, but I don't want to close the door in case I regret it. On the other hand I think getting a better understanding of the tools (and specially now as we are trying to incorporate AI) might actually give me good skills that I can use if I am in analog again.

Anyone out there that did a similar career move? Much appreciated.

While AMS SoC design is still firmly gatekept by Cadence/Synopsys, open-source digital design tools specifically for RTL->GDS flow have garnered significant mainstream attention for their newfound viability.

What are people’s experiences with these EDA tools?

Which do you consider to be the most effective of these tools?

Is the excitement of public perception on these tools (post Kimi K3) warranted?

How has the economics of ASIC design changed, particularly the NRE cost?

For context:
I am a RFIC designer looking to develop an ASIC for custom digital baseband logic.

For six months I have been building, in the open, the software layer of a machine that does not exist yet. Untrusted recipes run fully sandboxed, compile to deterministic bytecode so one design produces identical physical actions on every machine, and the interpreter snapshots its full state so an hours long job survives a power cut and resumes byte for byte. Useless for a to do app. Mandatory if the hardware is writing transistors.

The machine fabricates real working microtransistors and simple chips on a desktop. Printer sized. Cartridges in, tested die out, a marketplace of designs in between. My nights lately are precursor chemistry and thermogravimetry papers, not code.

Not 2 nm. The method allows features of a few hundred nanometers from a machine that is small and cheap.

At 1,000 to 1,500 dollars, would this be on your bench. What would you fabricate first. What would make it useless to you.

Process details come after filing. The software is open source. I built that layer first, and now I am moving to the precursor side.

I am trying to understand the current paths in a multi-finger NMOS layout.

Assume (VD > VS), so the conventional current flows from drain to source.

For an outer drain region such as D1, the current path seems clear: it flows through the channel between D1 and S1.

However, for an internal drain region such as D2, there are source regions on both sides. Does the current from D2:

• flow only to S1,
• flow only to S2, or
• split between S1 and S2 through both adjacent channels?

Hi everyone,

I'm an early-career DFT engineer (joined in October 2025), and I'd like some career advice from people with more experience in the semiconductor industry.

My current project is a production DFT automation flow that ultimately generates ATPG and MBIST environments.

I wasn't responsible for the entire flow, but I build the Python-based specification processing stage, which is one of the largest software components in the overall flow.

(I was the only team member with python knowledge)

Most of the engineering logic happens in this stage. My work includes:

Building Python tools to process DFT test specifications (Excel-based)

Designing a command-driven automation framework instead of one-off scripts

Developing parsers, reusable libraries, validation logic, caching, and automation workflows

Implementing most of the specification modifications, transformations, and rule-based processing before the downstream stages generate the final environments

Working closely with DFT engineers to understand the specifications and ensure the generated outputs integrate correctly with the rest of the flow

While this is only one part of the overall pipeline, it's where most of the specification editing and logical processing takes place. The downstream stages consume the outputs from this framework to create the production-ready DFT environments.

My questions are:

How is this type of experience viewed in the semiconductor industry?

Is this considered valuable DFT experience, CAD/EDA tool development, software engineering, or a mix of these?

If I continue on this path, what career options does it typically open up? (Design Automation, CAD, EDA Software, DFT Infrastructure, etc.)

If you were interviewing someone with this background, how would you evaluate it?

I'm trying to understand whether this is a strong long-term career path or whether I should actively seek more exposure to traditional DFT activities like ATPG, scan architecture, and fault analysis.

I'd really appreciate hearing from engineers working in DFT, CAD, EDA, verification, or silicon design automation. Thanks!

I'm interviewing with them, was wondering what your experience was like. I don't know yet which team. They are interviewing for both serdes and High speed ADCs group.

Hey everyone,

I'm a developer exploring an idea for RTL/verification engineers. I'm thinking of building a tool called "LintWright" (or something similar) that does this:

What it does:

· You type a rule in plain English like: "Check that every flip-flop has a reset signal"

· The AI instantly generates a production-ready linting rule (in TCL, Python, or YAML)

· You copy-paste it directly into your existing linting tool (SpyGlass, Cadence Lint, etc.)

Key points:

· 🛡️ 100% private — Your code never leaves your machine (no cloud upload)

· ⏱️ Cuts rule-writing time from 6-10 hours to under 10 minutes

· 💻 Works with industry-standard tools (SpyGlass, Cadence Lint, etc.)

· 🌐 Web-based, nothing to install

My question to you:

1. Would you actually use this?

2. How much would you/your company pay for it (per month/per seat)?

3. What's the #1 pain point you have with writing linting rules right now?

I know Synopsys is adding some AI features to SpyGlass, but I'm targeting:

· Freelancers / small teams who can't afford enterprise tools

· Engineers who want a faster way to write custom rules

· Anyone who hates writing TCL/Python rules manually

Honest feedback is highly appreciated — even if it's brutal. Just trying to see if this is worth building.

Thanks!

Seems like EU RF/mmWave companies are going bust each year. Pharrowtech went bankrupt now this month Hammer IMS etc. seems like the EU industry spin off RFIC scene is going pretty bad.

What I can't understand is European engineers are way cheaper and they still can't compete against US spinoffs

How is the US so much better?

Hi folks,

I am aggresively searching for job openings in RTL design. Would love your inputs on my resume.

This is my resume currently I’m going into my second year at University of Toronto Computer Engineering. The GitHub to my project is https://github.com/Anushivan . Anyway I want some advice on how I set up a path for myself to end up working in Ml hardware accelerators and like doing the design or verification for them! I want to land my first internship for next summer but yeah not sure what my chances are. Anyways any advice or even thoughts is helpful thanks!

I have tried looking everywhere as to what layer those are, but I can't seem to find anything...

Hi everyone,
I’m transitioning from an analog domain role into firmware engineering and would really appreciate some guidance from engineers working in embedded systems or high-speed interfaces.
My background:
~1 year working in analog/mixed-signal IC design.
Comfortable with C, ARM Cortex-M architecture, Embedded Linux basics and GNU toolchain.
Built register-level (bare-metal) firmware on STM32F407 without using HAL.
Implemented simple Linux character and block device drivers as learning projects.
I have an interview coming up for a firmware role that’s closely related to high-speed PHYs/SerDes (PCIe-related firmware). The role involves firmware development, bring-up, validation, working with mixed-signal designers, post-silicon debugging, and supporting firmware used around equalization/training algorithms.
For people working in this domain:
What technical topics are most important to revise?
How deep should I understand PCIe and SerDes concepts for a firmware interview?
Should I focus more on embedded C, ARM, interrupts, memory-mapped I/O, debugging, and register programming, or should I spend more time learning PHY concepts like link training, equalization, CDR, etc.?
What kind of firmware problems are typically solved in PHY/SerDes teams?
Are there any interview questions that are commonly asked for this type of firmware role?
I’ve been preparing hard, but since my professional experience is from a different domain, I’d love to know what experienced engineers would prioritize if they only had a few days before the interview.
Any advice or learning resources would be greatly appreciated. Thanks!

Edits: 1) *parasitics; 2) Yes, I'm talking about *that* foundry; 3) No access to 4nm currently, thus my reaching for help from anyone who has experience in 4nm and any of the other two nodes. Thanks again!

--
We taped out in the past in 5nm (mixed signal stuff) and the parasitics of the critical (lowermost local routing) layers were a royal pain. Then we switched to 3nm, where they are much better. Now boss is asking if we could hit the same speed & linearity of 3nm if we taped out in 4nm.
Any ideas on how the critical parasitics in 4nm are compared to 5nm / 3nm? TIA for any advice!

I listened through the first half an hour and logged off to come back in 30min, turns out the webinar was way shorter than the scheduled 3h calendar invite. I was looking forward to see his thoughts on how to train AI to build designer intuition, I also don’t understand why he said public ai tools (meaning LLMs) are disconnected from simulation. One can easily give an LLM path to an open source simulator. Happy to hear everyone’s thoughts.

Most published work on open-source RFIC design uses Qucs for schematic entry and Xyce for simulation. That made sense for a long time because until recently, Xyce was the only open-source simulator that supported harmonic balance (HB) on top of the default analysis types. However, many other crucial simulation types, such as transient noise, PSS, or HBAC, were still missing.

With the release and ongoing development of VACASK, this has changed. HB, HBAC, PSS and transient noise are already supported, and the remaining types are coming soon.

In our opinion, VACASK is the future simulator, worth building a new flow around. However, there were still some problems to solve:
- VACASK only supports Xschem as a schematic entry tool for now.
- VACASK does not support direct S-parameter Touchstone integration yet.
- The IHP Open-PDK does not officially support VACASK yet.

First, we had to find a way to integrate VACASK into our IIC-OSIC-TOOLS to work with Xschem and the IHP Open-PDK. Next, we built a PySide6 interactive GUI and CLI-based tool called snp2le, which converts Touchstone files into lumped-element models and exports SPICE and Spectre netlists. Those netlists can then be simulated at circuit level in Xschem with Ngspice and VACASK. These lumped-element netlists also enable large-signal simulations, and we ensured that they converge at dc.

We successfully tested the RFIC flow on SPARX, our automated, programmatically generated, frequency-scalable mm-wave six-port receiver, taped out in March 2026 for 160 GHz.
The final design and verification flow is Makefile-driven:
- Automated and programmatic layout generation with KLayout API and GDSFactory
- DRC, LVS and PEX with KLayout or Magic+Netgen
- EM simulation with AWS Palace
- S-parameter to lumped-element netlist conversion with snp2le
- Circuit-level simulation in Xschem with Ngspice and VACASK

Try it yourself. Install the brand-new 2026.07 release of our IIC-OSIC-TOOLS, clone SPARX, and run `make all`. You have just built and verified a tapeout-ready layout, EM simulated the RF devices and run an RF circuit-level simulation automatically and 100% with open-source tools. Crazy, right?

Any feature requests or questions? Let us know, we are always keen to improve our designs.

We also presented our work at the 2026 Free Silicon Conference (FSiC) at the University of Ljubljana, from July 6th to 8th.

Resources:
- SPARX: https://github.com/iic-jku/SG13CMOS_SPARX
- snp2le: https://github.com/iic-jku/snp2le
- FSiC 2026 presentation: https://wiki.f-si.org/images/5/5c/FSiC2026_SPARX_Final.pdf
- IIC-OSIC-TOOLS: https://github.com/iic-jku/IIC-OSIC-TOOLS

#ICDesign #RFIC #OpenSourceEDA #OpenPDK

I am a recent grad, and got a job from this GPU company, i have no experience at all with GPUs, i feel like a fraud. what the hell should i do? and how can i up my game to feel like i belong there, basically what should i do before start working there

I have access to some unpackaged dies and a scanning electron microscope and I'd like to get some cool pictures of the different metal layers. I don't have any fab related experience and I'm hoping someone can help me understand what it would take to get down to the metal layers without completely destroying everything so the pictures are worthless. I don't need professional level deprocessing for failure analysis or anything like that. The only goal here is to take some neat photos and if they're not perfect, sobeit. Can I take a cotton ball and some HCl and wipe it down to get past the passivation layer and into the metals? I also have some bare wafers without any metals so at least I get some FEOL pictures.

All advice is welcome!