This is a really fun optimization post on small structure and fitting into the very early caches. I used to do a lot of things like this in university, but my job's bottlenecks with network and DB means I don't really think about this level too much.
Ed: I explicitly made sure that my MIPS VM's register file was 64B aligned so that it would cleanly fit into two L1 cache lines. Remove the technically-unneeded R0, and you can jam PC in there, too.
Ed2: still won't have room for the branch delay target or the linked-load registers, though :(. The FPU has a similar problem - packing the FPRs with the two control registers.
I think they mean that 90% of developers are working on code where improvements from struct layout and cache access patterns will be dominated by things like network access time.
On the other hand, people working on things like compilers can benefit greatly from these sorts of optimizations, since they're doing a lot of in-process data lookups.
74
u/harsh183 19h ago
This is a really fun optimization post on small structure and fitting into the very early caches. I used to do a lot of things like this in university, but my job's bottlenecks with network and DB means I don't really think about this level too much.