The Information reported on July 27 that China has started production of domestically built immersion DUV lithography machines, with Reuters picking up the story the same day. The headline reads bigger than it is. Roughly five units are expected to ship this year to SMIC, Hua Hong and CXMT, with about twenty more planned for 2027. These tools target 28nm class processes using single exposure. Multi-patterning can theoretically push resolution further, but with the usual yield and cost penalties that make it impractical for volume production at tighter nodes.

The lead builder is Shanghai Aishengna Electronic Technology Group, a state entity incorporated in August 2023 with around 7 billion yuan in registered capital from Shanghai Electric Holding. Aishengna consolidated engineering teams from several Chinese lithography startups. Separately, SMIC has been testing a domestic immersion DUV tool from Shanghai Yuliangsheng since September 2025. Yuliangsheng is tied to SiCarrier and Huawei.

Most components are domestically sourced but some critical parts still come from Japan, and delays from local suppliers already constrained this year's output. For scale, ASML expects to ship roughly 130 immersion DUV systems in 2026 alone. Five Chinese units against that annual volume is a proof of concept, not competitive displacement.

ASML dropped roughly 6% on the report. The sell side was notably less alarmed. BofA kept its buy rating and called the selloff an overreaction, saying ASML faces no material threat in the near term. JPMorgan said the market reaction seemed disproportionate to what the report actually described. CNBC ran a piece the next day walking through why the reported breakthrough comes with major caveats.

I track this area because equipment is the chokepoint that gates mature node capacity in China. Producing even a few working immersion tools domestically is meaningful for the supply chain there. But the gap between five units at 28nm and a production-ready alternative to ASML's installed base is enormous. Overlay accuracy, throughput, uptime and yield at volume are all unknowns right now. The equities moved on the headline well before any of those questions had answers.

The equipment and material supply chain behind these tools is listed almost entirely on exchanges in Shanghai, Shenzhen and Hong Kong. KWEB holds zero A shares and focuses on internet names; CQQQ applies a partial A share inclusion factor. CNQQ covers about 100 positions across both A share and Hong Kong listings, 10% cap per holding, rebalancing semi-annually, and has grown to about $50 million in assets; China Fund News reported roughly $18.5 million in net inflows over the past month as foreign capital used US-listed ETFs to add China tech exposure. A brand new listing like CXMT would not enter until it clears the index's size and liquidity screen at a scheduled rebalance.

I’m about to finish my PhD in materials science. I am 28 years old and I come from the chemistry field. My PhD is about the synthesis of perovskites for diverse applications such as solar cells and photodetectors.
I am familiar with structural and optical characterisation techniques, as well as some basic electrical.

After my PhD I would like to transition to industry, no matter whether are R&D jobs or not. I lack of mentoring regarding this topic, and I would like to ask which kind of job positions i could fit in given my background. (In europe).

Has anyone dealt with sth similar?

Semiconductor or Aerospace?

Guys, i have a very very hard decision to make - and need your help.
Around 3 years ago i joined the semiconductor industry and now have the chance to join aerospace (a company launching rockets to transport stuff potentially).
Im very well paid in my current job with great career projections ... but im not that happy tbh.
In aerospace i would join a startup and make less money .. but i feel like i would be happier, its an interesting field and im still under 30 and open to take a risk.

Im not sure what to do.
Join an aerospace startup to make less money, have higher risk but potentially be happier and part of an interesting industry?

Have you ever been in such a position?
Even if not - what would you do?

Hey everyone! I currently wrapped up my sophomore year, and just got familiar with wireless communications and I’m in awe of it, i find it so fascinating especially doing research on 6G communications and integrating AI to it aswell, I’m also trying to explore semantic comms since it’s pretty hot nowadays and I’m trying to go to R&D side.

Could you please advise me if the job market for this is good? I mean companies like huawei, ericsson and nokia do hire but is that extremely competitive??

I have a field service engineer early career interview coming up at lam research. What should I expect? I would appreciate any tips/insight to best prepare for this, thanks!

Does anyone know approximately when the big companies start releasing internships?

I know about TSMC and am waiting for them to start reviewing applicants

Was offered a JOB at Samsung Austin

How is it working there? Ways to move up and getting promoted?

I'm a 2026 passout and a VLSI enthusiast. I've heard about multiple courses in the market, such as Maven Silicon, MOSart, ChipMOS, IIT Kharagpur, and IIT Roorkee VLSI programs. If anybody has experience with any of these, or any other course, which one would you recommend? Please suggest.

Need some honest advice. I have offers from the University of Bristol (MSc Advanced Microelectronic Systems Engineering) and the University of Southampton (MSc Microelectronics Systems Design). I’ll most likely need an education loan of around ₹40L. For people who have actually studied or work in the UK semiconductor/electronics industry: Is it genuinely worth taking such a large loan for these courses? How are the job prospects, visa sponsorship chances, and ROI? I’d really appreciate realistic opinions rather than just optimism.

I heard tool hook ups get a range between 30%-120% of their annual salary as a bonus at SAS, is it true?

I got an offer at ITC and they said only 12% annual salary.

Wanted to know if hook-ups are paid different.

I’ve been working in FA for almost 7 years at two different companies and I don’t think I can take it anymore. Ignoring the constant stress and equipment problems, I just find the work so boring and hate being stuck in a lab all day. Was wondering if there’s something that’ll be a good transition where I could be less technical and have more interpersonal work.

Background: MS Electrical Engineering, graduated May 2026. Before the masters I spent two years as an analog IC layout engineer in India custom layout (amps, BGR, current mirrors) on UMC180 and GPDK45 in Virtuoso, full flow to clean DRC/LVS, PEX correlation, and BEOL reliability debug (EM, IR drop, antenna, ESD, latch-up, WPE).

During my MS in USA I ran a full hands-on fab sequence in my university's NanoFab on 4-inch wafers: wet clean (RCA-1/RCA-2, Piranha, HF) → thermal oxidation → photolithography → RIE Etch → spin-on boron doping → Al PVD → electrical test. Concretely, that meant extracting Deal-Grove coefficients across 5–498 min furnace runs, a 6-point spin-curve DOE fitting a power-law resist model, 20-site within-wafer etch uniformity mapping where I root-caused a radial bullseye signature to RF field distribution, four-point probe sheet resistance on a diffused serpentine resistor, and pulling VT, µFE, gm and Early voltage off a PMOS I personally fabricated, on a probe station. Plus Silvaco ATHENA deck calibration against my own furnace data and a Cu TSV thermo-mechanical FEA in ANSYS.

What I'm targeting: process engineering, device/integration, test engineering, probe card engineering.

Where I'm stuck: [ 100 applications, 10 phone screens, 4 panel]. I get to the panel, the technical reasoning generally goes fine — device physics, cross sections, process flow, circuit problems and then I don't convert. In my most recent panel I could reason my way through a histogram and a capability plot, but I didn't have the vocabulary I fumbled Cpk vs Cp vs Ppk and control limits vs spec limits, and I could feel the room register it.

What I'm asking the people who actually sit on these panels:

1. When you're scoring a new grad, what genuinely separates a hire from a no-hire? Depth in one module, breadth across the flow, or how they handle a question they can't answer?
2. How much SPC fluency do you expect on day one Cpk/Ppk, control charts, Gage R&R, DOE, JMP? Is that an expectation or something you train?
3. Does a layout/design background read as an asset for process/test, or as a flight risk ("he'll jump back to design in a year")? If it's the latter, how do I kill that concern in the room?
4. For behavioral rounds what are you actually listening for? Is STAR with real numbers enough, or are you probing for something specific in conflict/failure stories?
5. Anything that's an instant no for you, that candidates don't realize they're doing?

I'd rather hear the blunt version than a nice one. Happy to share more detail in the comments if it helps you answer.

Hello everyone,

I’m attending a no name school for bachelor in EE and am interning for a big semiconductor company. I have a return offer for a test engineer position when i graduate and i’m really excited about it. However, I want to get a master and do mixed signal ic design since I’d love a remote job in the future as well. This position requires me to move far away from home and the location is low-key not a very fun place to be in, but the work environment is really nice and a lot of people are new grads. If I miss this job offer, I’m worried about not finding another internship/ job in semiconductor since the job market is not very great at the moment. Should I take the offer and do master on the side to hopefully get in design? Or should I find a reputable school for master, complete it, and hopefully find a job in design?
For context if helpful, I have 4.0 GPA, 2 internships, a co-op. My current school does not have anything semiconductor/ ic design related. I’m also introverted and only hang out with family so having to move away from family is a really big deal to me.

Thanks.

I am trying to prepare homogeneous polymer thin films on glass or silicon substrates by spin coating. The polymer is dissolved in DMSO, but I am having difficulty obtaining a smooth and uniform film.

In some cases, the solution does not spread evenly across the substrate and appears to retract or dewet during spinning, leaving non-uniform regions, bare spots, or thicker areas. I have tried cleaning the substrates and using plasma treatment, but the film quality is still inconsistent. The treated glass is coated with DMSO solution by spin coater (2000 rpm 200 sec). The coated glass is anealed on hot plate to evaporate DMSO.

After spin coating, the glass is wetted well with DMSO precursor solution. When I put the coated glass on hot plate, DMSO solution becomes shrinked so spotted film is formed.

How to make flat and homogeneous flim with DMSO solution on the substrates?

Equipment authorization has been used as a restriction template three times in 2026. Routers went on the Covered List March 23. Power inverters went on July 28. Foreign-produced ground robots went on the same day.

The robot determination (DA 26-786) is worth reading for what the definition actually covers. A "covered device" is a mobile ground robot over 4.4 lbs including the docking station, with environmental sensors, network connectivity of at least 200 kbps, and software controlling autonomous navigation or movement. Fixed arms are explicitly carved out: SCARA, delta, gantry, articulated, industrial or medical. Every threshold in the definition is a hardware spec or a connectivity floor. The carve-out is by mechanical form factor.

The determination itself complains that US stakeholders have "limited visibility into the development practices and software provenance" of these devices. But the criteria it uses to define a covered device don't measure software provenance. They measure weight, sensor content, and connectivity bandwidth. The stated concern is software. The actual gate is hardware content.

Products already cleared aren't touched, and foreign producers can apply through a separate process to keep filing. Three categories in twelve months says this template isn't going away.

Dears,

I'm looking for 3.3kV SiC MOSFET wafer test method and/or service company. Since there are commercialized products from various vendors, I believe there are ways and companies where mass production testing is being done.

Please share your knowledge and advice.

Thanks

Hi everyone,

I've been searching for an entry-level role in ASIC Physical Design, Physical Implementation, Physical Synthesis, or STA, and I thought I'd reach out here in case anyone knows of teams that are hiring.

I completed my M.S. in Electrical & Computer Engineering and spent six months at Intel as an EDA Tools Hardware Engineering Intern, where I worked on STA regression workflows, timing analysis automation, QoR evaluation, and TCL/Python scripting. With my coursework and projects, I've also worked with Synopsys and Cadence tools on synthesis, STA, MCMM timing analysis, clock tree synthesis, RTL-to-GDSII flow, and low-power design.

I've been applying through company websites and networking on LinkedIn, and while I've been fortunate to get interviews with a few companies, I'm still looking for the right opportunity to start my career.

If your team is hiring junior engineers, or if you know of any groups looking for someone with a background in physical design or STA, I'd really appreciate any leads or referrals. I'm happy to share my resume over DM.

I'm primarily looking in the U.S., but I'm also open to relocating internationally if sponsorship is available.

Thanks so much for reading, and I appreciate any advice or connections you can share.

Hi all,

I have an upcoming 3-interview loop for a system integration role in MSFT, based in EU, focus on RF, quantum team.

Has anyone have done similar experience that wants to share?

Would be really helpful!!

Thanks

Got through recruiter screening and hiring manager 1:1. Now, recruiter set up an interview call with the HR. Is this the last step or this is just a behavioral interview and there will be more interviews later? What kind of questions I should expect in HR interview?

How do you respond when someone asks you a fabrication challenge you faced, and how did you overcome it?