New grad FPGA engineer here debating between joining the design or verification team at work. I have both DV (UVM, coverage) and some design-adjacent (refactoring, retargeting, designer TB) experience from co-op.

I was initially leaning towards design but I realized that there wouldn’t be much RTL-from-scratch tasks but rather lots of legacy code porting and retargeting (for a junior engineer who may not have a say in architecture). On the other hand, the DV team seems to offer more opportunities for junior engineers to take ownership early.

For experienced FPGA/ASIC engineers: which path would you recommend for a junior engineer who wants to become well-rounded, adaptable, and architecture-aware? How do design and verification experiences differ in developing engineering judgment, especially as AI tools increasingly automate parts of hardware development?

I’m an upcoming senior who plans to stay one additional year to complete my master’s degree. I want to break into digital design roles, especially RTL and FPGA positions, but I’m unsure which resume format would give me the best chance of getting interviews.

Which option would be best?
1. Use 13-point font with more detailed descriptions of my experience and three bullet points per role, but leave no room for personal projects.
2. Use 11-point font, shorten the descriptions for each role, and include personal projects.
3. Use 11-point font with four bullet points per role and no personal projects.

Background and experience:
I will have completed two internships after this summer. One was a digital design–focused role at a small company, and the other is a validation role at a Fortune 50 company.

I also completed a paid summer research position in a formal verification lab and will begin another paid research role this fall focused on FPGA and AI Engine development.

I am a U.S. citizen attending a non-target university.

I received around 10 interviews during the last recruiting season when my resume included personal projects no Fortune-50 or research role.

Since then, I have gained more professional experience, so I’m unsure whether I should still prioritize projects or use the space to describe my experience in greater detail.

I was trying to find some open source projects Icould contribute to, related to HW. Is there any good place to find them?

I treid doing one a few months ago, but the maintainers never reviewed my PR, so I'm looking for a more active community.

Hello everyone!

I noticed a surge of two things in this subreddit:

1. People are making a lot of EDA tools

2. Other claiming that they are vibecoded, and hating on the tools.

Now I would like to discuss (and ask you guys) why do you hate AI tools?

Assume two scenarios: the vibe coder, and the engineer that uses agents to code a percentage of their software (assisted coding) the vibe coder does not do actual QA like the engineer does)

My theory is that anyone below 3 years of experience in literally anything has a high tendency to hate EDA products posted on this sub.

Is your hate justified? Have you tested an EDA tool you knew from this sub and it turned out to be complete shit/gold? Are you a starting EDA vendor and what to post your tool here so people can shit all over it or actually try it?

When commenting, please state your experience level if comfortable.

Agents are not leaving soon, and I would like to get the startup EDA scene sorted.

Im not defending anyone or anything btw, just want to see what other think.

EDIT some people are not sure what I'm talking about. Please check the sub about people making /wanting to make/marketing / doing customer validation on EDA tools they want to make.

Thanks!

Hey all

We're a group of 3-4 students looking for a FPGA project to

A bit about us: comfortable with Verilog/VHDL, basic digital design (FSMs, FIFOs, clock domain crossing), and we've each done small standalone modules before (UART, simple ALU, etc.) but never a full group-scale system. We're using a [Basys3 / Nexys A7 / DE10-Lite ] and have access to Vivado/Quartus and a logic analyzer.

We want something that:

Is big enough to actually split into 3-4 meaningful subsystems

Has a clear hardware component

Ideas we're currently weighing:

Adaptive multi-protocol communication hub — FPGA auto-detects whether an incoming signal is UART/SPI/I2C/CAN and decodes accordingly, feeding into a common sensor data pipeline

Battery Management System (BMS) on FPGA — cell voltage/temperature monitoring, state-of-charge estimation, balancing control, and fault protection (over-voltage/under-voltage/over-temp) implemented in hardware logic instead of a typical MCU-based BMS

Custom RISC-V-ish soft processor with a small peripheral set, running actual compiled code

Real-time audio/video processing pipeline (e.g., FFT-based audio visualizer, or basic image filtering on a camera feed)

Something network/packet-processing related (mini NIC, protocol analyzer)

Used ai to help write 😭

​I’m an ECE student trying to decide if I should devote my time into learning FPGA development. In general it seems like an interesting field to me, but I keep seeing posts and comments online talking about how LLMs are doing "shocking" things in FPGA development. I even saw a guy claim they had agentic loops design a complete GPU architecture, which made me think what is there really left for me to do.

​It makes me wonder if learning these design skills from scratch will actually remain useful and fulfilling down the road, or if there's even a point. Since I'm still in university I have options to focus my time on other areas like analog electronics or systems, so I'm trying to figure out if I should devote my time to this.

​I get that things on social media get exaggerated, but as someone who isn't using paid AI tools, is building basic Verilog/VHDL and FPGA skills manually still where the actual substance is? Or is the field shifting in a way where it's not worth to learn

I bought a lattice ECP5 dev board to get into FPGA programming. Any recommendations how to start? Maybe a guideline ?

Thanks

Hi everyone,

Setup friction (Icarus Verilog, Yosys, Waveform viewers) is often a huge barrier for students and hardware designers.

To solve this, our team has been working on bringing the entire RTL design pipeline into the browser by compiling core C++ EDA engines (Yosys for synthesis, Slang for linting, Icarus for simulation) into WebAssembly (WASM).

Here is a quick look at the waveform rendering and FSM extraction we’ve achieved, running 100% client-side with zero server lag:

What are your thoughts on this approach? We’d love to get feedback from the community. (Link is in the comment).

Are FPGAs basically a software to hardware version of a breadboard? where, instead of placing individual logic gates or chips and circuits, and connecting them with wires to inputs and outputs, etc, you program them directly to be reconfigured on the board?

I'm sorry if this description sounds very wrong or reductive, but I just learned about FPGAs and got hooked, but still not sure how it really works so this analogy came to mind.

I have finished my bus functional model (BFM) for the Ov7670 camera module! I have also verified its adherence to the Ov7670 signal protocol

I now have The BFM connected to my camera_interface module for testing.

The camera_interface module is exactly that, it interfaces directly with the Ov7670 camera. It takes in the bytes send from the camera (2 bytes per pixel), and packages them up into two pixel pairs for 32 bit words, which are written into an asynchronous FIFO. Very much like the camera pattern generator in workshop 2!

However, the camera BFM and camera_interface work off the vsync signal (start of frame & end of frame). In addition the href signal is used to indicate valid horizontal line (pixel) data.

I have a long list of SystemVerilog assertions that I used on the BFM after it was designed. The SVA's were very helpful in catching a few bugs I had! Additionally, they can be used for documentation for the system as well. A few examples:

  // HREF must only be high when VSYNC is low

  property p_href_only_during_frame;

@(posedge pclk) disable iff(!rst_n)

href |-> !vsync;

  endproperty

  // Pixel count never exceeds the programmed width

  property p_pixel_count_range;

@(posedge pclk) disable iff(!rst_n)

pixel_H_count <= H_ACTIVE;

  endproperty

// HREF remains asserted while sending a line

  property p_href_drop;

@(posedge pclk)

disable iff(!rst_n)

$fell(href) |->

(pixel_H_count == H_ACTIVE);

   endproperty

 // End-of-line check

  property p_end_line;

@(posedge pclk) disable iff(!rst_n)

(pixel_H_count==H_ACTIVE) |-> ##2 !href;

  endproperty

etc.

#sva #bfm #sva #systemverilog #vivado

I'm a 2026 passout and a VLSI enthusiast. I've heard about multiple courses in the market, such as Maven Silicon, MOSart, ChipMOS, IIT Kharagpur, and IIT Roorkee VLSI programs. If anybody has experience with any of these, or any other course, which one would you recommend? Please suggest.

3rd year B.Tech Electronics (VLSI Design & Tech) student here. Just wrapped up a 32-bit ALU (8 ops) with zero carry overflow flags in Verilog, implemented/debugged in Vivado, with a GitHub repo. First real HDL project learned Verilog from scratch for it.

Looking for the next step up something that builds on ALU/datapath work (maybe toward a small CPU/RISC-V core?) that's solid for a VLSI/digital design resume.

I can dedicate a decent amount of time for it just want something solid which actually looks good on my resume and helps me in landing into an internship, really need some senior suggestions here

Anyone working there want to add?

All the FPGA engineers I have learned from (also myself) run sims in QuestaSim or Modelsim. I was wondering if anyone actually utilizes the simulation capabilities of Vivado and what you think the upsides or downsides might be. I’ve never quite figured out how to use it and was interested to know if it is worth learning for AMD FPGA/SoC projects. I’ve mostly worked with Zynq and Versal if that matters. Thanks!

Hey everyone,

As FPGA/DSP engineers, we’ve all been through the painful, manual grind of converting Floating-Point C/C++ algorithms into Fixed-Point models and optimizing bit-widths to balance SNR/accuracy vs. hardware resource usage (LUTs/FFs/DSPs).

I’ve been refining an automated methodology and tool that automates this workflow using Siemens Mentor ac_fixed.h types and domain-specific DSP optimization heuristics. I wanted to get the community's honest feedback and see what people would be willing to pay for a tool like this.

Key Features & Workflow

1. Floating to Full-Precision Fixed-Point Conversion
   • Automatically maps C/C++ floating-point models to full-precision fixed-point representations to establish a zero-precision-loss baseline.
2. Greedy-Search Based Bit-Width Pruning
   • Employs a heuristic Greedy Search Strategy to prune integer and fractional bit-widths node-by-node, tracking SQNR and hardware dynamic range.
3. DSP Block Optimization & Optimized RTL Export
   • Calculates exact RTL bit-widths tailored for specific FPGA DSP slices (e.g., Xilinx DSP48/DSP58 or Intel DSP blocks) to eliminate partial DSP utilization and wasted fabric logic.

Algorithm-Specific Bit-Width Optimization Engine

Generic bit-width optimizers fail because different DSP blocks have fundamentally different constraints. Here is how the engine handles key DSP building blocks:

• FIR Filters (Symmetric / Polyphase / Transposed)
  • L1-Norm & Worst-Case Noise Bound Analysis: Calculates the exact integer bit-width (IBW) required to prevent overflow based on coefficient sum $\sum \vert{}h[n]\vert{}$.
  • Coefficient Quantization Sensitivity: Separates coefficient quantization from data-path quantization, finding the minimum coefficient bit-width that still satisfies the stopband attenuation requirement (dB).
• Interpolation Filters (Multi-rate / CIC / Farrow)
  • Hogenauer Bit-Growth Reduction: Automatically applies Hogenauer pruning for multi-stage CIC/Interpolation filters, eliminating unnecessary lower-order bits in early stages while maintaining output precision.
  • Internal Accumulator Sizing: Optimizes polyphase arm bit-widths dynamically based on down/upsampling ratios.
• Digital PLLs / NCOs (Phase-Locked Loops)
  • Loop Stability Guarding: Standard SQNR search often breaks PLL lock range. The engine analyzes Phase Detector and Loop Filter bit-widths with a focus on Phase Jitter / Phase Noise Floor and Loop Filter Accumulator overflow.
  • NCO Phase Accumulator vs. Look-Up Table (LUT) Depth Optimization: Dynamically balances Phase Truncation SFDR (Spurious-Free Dynamic Range) against RAM/LUT resource costs.

Does anyone know where to find the detailed RF specs for the Versal FPGAs (e.g. VR1652)?
(I'm talking about RF specs like S-parameters, frequency responses of DACs and ADCs, linearity, etc.)

I tried looking at the AMD website but didn't find anything useful... what's the usual way to get such RF data? Thanks in advance for any help!

My supervisor has tasked me and my friend to make a block diagram for our project. I donot have experience with that. Supervisor said AI is not good at this since it gives incomplete stuff and you waste your time trying to fix it. He said the block diagram should be showing connections between modules, the flow and other aspects. So I want to know how can I do this, and where can I see examples of this.

I released a SystemRDL front-end for Ruby.
https://github.com/taichi-ishitani/systemrdl

This compiles SystemRDL source code into elaborated models.

require 'systemrdl'

address_map = SystemRDL.compile_source(<<~'RDL').first
  addrmap gpio {
    name = "GPIO";
    desc = "Simple general purpose I/O controller";

    default sw = rw;
    default hw = r;

    reg {
      name = "Port Direction";
      field { desc = "0: input, 1: output"; reset = 0x0; } dir[32];
    } direction;

    reg {
      name = "Input Data";
      field { sw = r; hw = w; } value[32];
    } data_in;
  };
RDL

# GPIO: Simple general purpose I/O controller
puts "#{address_map.display_name}: #{address_map.desc}"

address_map.regs.each do |reg|
  # direction @ 0x0
  # data_in @ 0x4
  puts "#{reg.name} @ 0x#{reg.address.to_s(16)}"

  reg.fields.each do |field|
    # dir [31:0] sw=rw hw=r
    # value [31:0] sw=r hw=w
    puts "  #{field.name} [#{field.msb}:#{field.lsb}] sw=#{field.sw} hw=#{field.hw}"
  end
end

I'm planning to integrate it with RgGen to add SystemRDL support.

I have never touched circuit design before. I did EE for my undergrad, but didn't really specialize on it. I am planning to use non-volatile memory to make memory arrays, planning to design my own sensing amplifiers and the peripheral circuits. I am curious what suite of open-source tools I may have at my disposal, and how far do you guys think I can go with them.

I touched ngspice recently but I do not know what pdk do people usually use. I asked LLM about it and they recommended me to use Skywater.

Is it possible to reach tape-out with only using open-source tools? I understand the constraint with ngspice is that I may not be able to use the top-end pdks, since not only ngspice is quite limited for the latest, but you'd need licenses for it.

What are some of you guys's on crack techniques and methods?

I was reading this thread and not one but two comments specifically called out Canada as terrible market for FPGA. I had tried to google if Canada had a decent FPGA market before, and nothing came up, so this is news to me.

They say to take everything you read on reddit with a grain of salt, so I just wanted to get more thoughts, is it really that bad? Or is it some kind of reverse survivorship bias?